Tz-Ching Yu

I'm a PhD student at Verification and Computer Architecture lab. I generally find myself thinking about problems related to verification of hardware designs. In the past, I spent some time working on verifying information-flow properties of processors through model checking and correctness of hardware designs in interactive theorem provers, such as Rocq and Lean.

Outside of research, I like skiing.

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Publications

  1. Towards Composable Proofs of Cache Coherence Protocols
    Martina Camaioni, Yann Herklotz, Tz-Ching Yu and Thomas Bourgeat
    Proceedings of the 15th ACM SIGPLAN International Conference on Certified Programs and Proofs, 2026
  2. RePIM: Joint Exploitation of Activation and Weight Repetitions for In-ReRAM DNN Acceleration
    Chen-Yang Tsai, Chin-Fu Nien, Tz-Ching Yu, Hung-Yu Yeh and Hsiang-Yun Cheng
    58th ACM/IEEE Design Automation Conference (DAC), 2021

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